Clock Gating and Precomputation Based Low Power ALU Design

Power reduction in dynamic circuits became an important factor today. In this thesis, we designs an ALU using the popular power reduction techniques named clock gating and precomputation based sequential logic optimization for low power . It reduces the power consumption by reducing the dynamic switching power. Power reduction deals with synthesis, design at circuit level and placement and routing stages, now moved to the System Level and Register Transfer Level. This is possible due to clock gating which always switch off the inactive unit of the design and reduce overall power consumption. The Register Transfer Level approach is always important because hardware designers generally verify power only at the gate level and any changes to the Register Transfer Level needs many design repetition to reduce power. Our designed ALU has 16 functions. Each functions will carries separate modules. This is because we need not to more than one operation at a time. When we use to operate one functional module, the other modules are not in use by the current executing instruction. At that time we will power off the other 15 modules by using the clock gating technique. Thereby we can reduce the switching power of the other unused modules. In the proposed system, we further modifies the clock gated ALU with another power consumption method of precomputation based low power architecture. The simulation is done by using Xilinx ISE 13.2 and we implement the design by using FPGA. KeywordsALU, Clock Gating, Dynamic power, FPGA, precomputation, RTL